1. Field of the Invention
The present invention relates to a semiconductor device and a semiconductor module mounted with the semiconductor device.
2. Description of Related Art
In recent years, ASIC (Application Specific Integrated Circuit) and DRAM (Dynamic Random Access Memory) are used on the inside of digital home electronic appliances in order to perform various information processing and control operations.
The ASIC and the DRAM are mainly connected in a one-to-one ratio. However, according to diversification of information processing and complication of control, there is a demand for an increase in the memory capacity of the DRAM in the same package (PKG). Therefore, in recent years, as shown in FIG. 1A, ASIC and DRAMs are connected in a one-to-two ratio. The ASIC is actuated to selectively control the DRAMs using a chip selection signal.
However, when the number of DRAMs connected to a transmission line of the ASIC increases, reflected waves (noise) generated from contacts with the transmission line in the DRAMs increase and the load on the transmission line also increases. This makes it difficult to design the ASIC and the DRAMs.
Specifically, when the DRAMs perform operations at a DDR (Double data rate), the DRAMs read and write data at both a rising edge and a falling edge of a reference clock. Therefore, a DQ signal (a data signal) operates at speed twice as high as that of other signals. The DQ signal particularly tends to be affected by noise. Similarly, a DQS signal (a data strobe signal) as a reference clock of the DQ signal is also present in the DRAMs after introduction of the DDR. Since the DQS signal operates at the same speed in association with the DQ signal, the DQS signal also tends to be affected by noise like the DQ signal.
Therefore, at least a DQ pin on the ASIC side and a DQ pin on the DRAM side are connected in a one-to-one ratio and a DQS pin on the ASIC side and a DQS pin on the DRAM side are connected in a one-to-one ratio as shown in FIG. 1B.
A semiconductor module having a simplex PKG structure in which only one DRAM is mounted on a PKG substrate is shown in FIG. 2A. In FIG. 2A, the DRAM has sixteen DQ pins and performs ×16 operation for inputting and outputting a 16-bit DQ signal. Pads on the DRAM and pads on the PKG substrate are connected in a one-to-one ratio. External pins drawn out from the PKG substrate to the outside and connected to an ASIC are represented by circles.
There is a semiconductor module having a structure in which plural DRAMs are mounted on a PKG substrate in order to increase the memory capacity of a DRAM while maintaining a connection state of the simplex PKG structure shown in FIG. 2A, i.e., the arrangement of the external pins (JP2006-024663A, JP2008-130184A, JP09-330589A, and JP11-339473A).
Among the semiconductor modules disclosed in these patent documents, an example of a semiconductor module having a structure called DDP (Double Density Package) in which two DRAM chips are stacked on a PKG substrate is shown in FIG. 2B.
In such a semiconductor module having the DDP structure, two DRAM chips that perform ×8 operation are actuated, whereby a package performs ×16 operation. Specifically, the package including one 1 GB DRAM chip that performs the ×16 operation is changed to two 1 GB DRAM chips that perform that ×8 operation. Consequently, the package can be changed to a 2 GB package that performs the ×16 operation.
In this case, as regards the DRAMs, it is costly to separately manufacture the ×8 operation chips and the ×16 operation chips. Therefore, a general-purpose DRAM that can switch the ×8 operation and ×16 operations is used to switch the operation state of the upper and lower DRAMs from ×16 operation state to ×8 operation state according to a bonding option or the like.
When the upper and lower DRAMs are caused to perform the ×8 operation, in order to realize a one-to-one connection of pads on the DRAMs and pads on the PKG substrate, concerning a DQ signal, DQ0˜DQ15 pads on the upper DRAM are alternately enabled (DQ0, DQ2, DQ4, DQ6, DQ8, DQ10, DQ12, and DQ14) and respectively connected to DQ0, DQ2, DQ4, DQ6, DQ8, DQ10, DQ12, and DQ14 pads on the PKG substrate. DQ0˜DQ15 pads on the lower DRAM are alternately enabled (DQ0, DQ2, DQ4, DQ6, DQ8, DQ10, DQ12, and DQ14) and respectively connected to DQ1, DQ3, DQ5, DQ7, DQ9, DQ11, DQ13, and DQ15 pads on the PKG substrate.
On the other hand, concerning a DQS signal, in the case of the ×8 operation, both the upper and lower DRAMs use DQS0 pads. Therefore, it is necessary to connect the DQS0 pads on the upper and lower DRAMs to a DQS0 pad on the PKG substrate. Since the PKG substrate is common to the upper and lower DRAMs, in order to connect the DQS signal without changing the external pin arrangement, one DQS0 pad on the PKG substrate has to be connected to the DQS0 pads of the upper and lower two DRAMs. Therefore, as a result, the PKG substrate and the DRAMs are connected in a one-to-two ratio. Therefore, only the DQS0 pad on the lower DRAM is connected to the DQS0 pad on the PKG substrate and the DQS0 pad on the upper DRAM is finally connected to a DQS1 pin (an external pin) by extending a wire on the PKG substrate. Consequently, a one-to-one connection can be realized.
However, as it is evident from FIG. 2B, although the positions of the DQS0 pad and a DQS1 pad are the same on the upper and lower DRAMs, the DQS0 pad and the DQS1 pad are arranged in positions apart from each other on the PKG substrate.
Therefore, concerning the DQS0 pad on the upper DRAM, after the DQS0 pad is connected to pad 1 provided on the PKG substrate anew, wire 2 from new pad 1 has to be extended to the DQS1 pin (the external pin). However, in this case, the inventor recognized that, in the upper DRAM, a signal path between the DRAM and the PKG substrate does not have substantially equal lengths for the DQ signal and the DQS signal of DQS0.